Partial product array multiplier

ABSTRACT

A multiplier comprising a partial product array means for receiving an m-bit multiplier and an n-bit multiplicand for generating a partial product array of numbers in a plurality of columns. Each of the columns is connected to a multi-operand adder capable of simultaneously adding m-bits.

United States Patent Singh et a1.

PARTHAL PRODUCT AR Y MULTWLHER inventors: Shanker Singll, Hyde Park;Ronald Waxman, Poughkeepsie, both of NY.

[73] Assignee: International Businew Machines Corporation, Armonk, NY.

[22] Filed: June 119, 1972 [21] Appl. No.: 264,082

[52] US. Cl. 235/164 [51] int. Cl. 606i 7/54 [58] Field of Search235/164 [56] References Cited UNITED STATES PATENTS 3,691,359 9/1972Dell 235/164 3,065,423 10/1962 Peterson 235/164 X 3,670,956 6/1972Calhoun 235/164 3,752,971 2 1973 Calhoun et al. 235/164 PrimaryExaminerMalcolm A. Morrison Assistant ExaminerDavid H. Malzahn Attorney,Agent, or FirmKenneth R. Stevens [5 7] ABSTCT A multiplier comprising apartial product array means for receiving an m-bit multiplier and ann-bit multiplicand for generating a partial product array of numbers ina plurality of columns. Each of the columns is connected to amulti-operand adder capable of simultaneously adding m-bits.

4 Claims, 9 Drawing Figures 11(8) mm/ND REGISTER 0(0) SHlFT REG.

HVE MULTI OPERAND ADDERS PATENTED 51974 SHEQW? m wE PATENTEU MAR. 5l974SHHFEUF? 2: mm 6E PAIENTED 51974 3.795.880

sum 5 ur 7 m N m N 2 m N 2 m N 2 m N 2 235 59 o o k & MAW k :3 2? mm mmo o o o 0 2% 2: NE SE 2: CE 2% O o c Q o 2: 2% AN? 3% SE SE 2: O Q Q o 0SE 2? AN? g 2% CE 2: O o o o o 8% 2? AN? 23 2% 2? 23 0 o O o 0 SE 2% AN?23 2% SE 8? o o o o O 2% 2? AN? A3 3? SE 2% C? c o o O c 83 2: AN; 33 3;SE x 2: 2% NE SE 2% SE 2: CE 2% BACKGROUND OF THE INVENTION Computersare traditionally designed to add only two numbers at a time. Someefforts have been directed to partial product multipliers but in knowninstances, these schemes are limited to two or three rows. In theconventional sense, multiplication is accomplished an iterative additionwith variations in the method of developing the final product. Theseapproaches require a minimum amount of hardware in that only onemultiplier bit is manipulated at a time. In some instances, the productof the low-order multiplier bit is multiplied with the multiplicand andthis result is added to a shifted product of the next higher order bitof the multiplier and the multiplicand. This result is stored and addedagain to the product of the third multiplier bit and the multiplicand,etc.

Some prior schemes attempted to increase to the multiplication speed byexamining simultaneously two, three and sometimes four multiplier bitsand manipulating these results with complex algorithms for shifting overzeros and for adding and subtracting appropriate amounts from thepartial sums as the multiplication takes place. Multiplication speedsare also increased by examining multiple bits of the multipliersimultaneously with appropriate addition and subtracting during amultiply cycle accompanied by shifting over zeros or ones of themultiplier, since a zero bit requires the addition of zero to thepartial sum.

Another conventional method of increasing multiplication speed is toprovide prefabricated multiples of the multiplicand; thus, for a setnumber of multiplier bits, tables corresponding to multiples of themultiplicand are employed, and an appropriate result is then gated to anadder circuit.

In all of these instances, speed is obtained by increasing the level andsophistication of the hardware. Obviously, hardware complexity isgreatly increased as multiplier systems attempt to examine more thanthree multiplier bits at a given time.

With the advent of large scale integration, it is now becomingtechnically feasible to modify the manner of addition and allow for theaddition of multiple operands, many times in excess of three operands,

SUMMARY OF THE INVENTION Therefore, it is an object of the presentinvention to provide a high-speed multiplier which allows for thesimultaneous examination and manipulation of many multiplier bits.

Another object of the present invention is to provide a high-speedmultiplier for performing an arithmetic multiplication with a moresimplified and less costly hardware implementation.

Another object of the present invention is to provide a high-speedmultiplier scheme which allows for a range of design variations as tocomputational time, hardware costs, and hardware complexity.

In accordance with the aforementioned objects, the present inventioncomprises a partial product array (PPA) means in combination with amulti-operand adder (MOA) for providing a high-speed multiplier.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of the preferred embodiment of the invention as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a chart illustrating theclassical pencil-andpaper or long-hand process of performing multiplication.

FIG. 2 mathematically illustrates the manner of arranging a partialproduct array in accordance with the present invention for specificallyhandling a 9bit multiplicand and a 6-bit multiplier.

FIG. 3 is a block diagram illustrating the manner of interconnecting theelectrical schematic diagrams illustrated in FIGS. 3A and 3B.

FIGS. 3A and 3B illustrate an electrical schematic diagram forimplementing the present invention with m n I register columns; i.e., anidentical number of columns as is required in the long-handmultiplication process counterpart.

FIG. 4 is a schematic block diagram illustrating a complete partialproduct array requiring p (m n)/(k) multi-operand adders, where I (m nl)/(k) l is an integer a m n-l/k.

FIG. 5 is a partial schematic block diagram and mathematicalrepresentation illustrating the manner of implementing a partial productarray requiring p register columns.

FIG. 6 is an electrical schematic block diagram illustrating in moredetail the manner of implementing the partial product array principlesillustrated in the partial block diagram and mathematical chart of FIG.5.

FIG. 7 illustrates a complete multiplier implementation utilizing thepartial product array of FIG. 6 in combination with a multi-operandadder, specifically illustrated for a 36 X 36 bit multiplier.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, anumerical partial product is generated in a partial product array (PPAThe partial product array receives an m-bit multiplier and an n-bitmultiplicand. Each column of the partial product array is implemented bya register with m-bit positions. In the maximum hardware case, m n Iregister columns are necessary. In the intermediate hardware case, onlyp register columns are necessary, where k is an interger which isgreater than or equal to log (m -l In this embodiment, k I one bit shiftoperations are necessary.

In the embodiment requiring m n l registers, each column result isapplied in parallel as inputs to an associated multi-operand adder. Thisembodiment requires maximum hardware. In the intermediate hardware case,each physical register column represents k columns of the partialproduct array. Thus, in a first addition cycle, for the intermediatehardward case, each column of the partial product array is applied tothe inputs of an associated multi-operand adder. The mathematicalresults are stored, and then the contents of the registers are shiftedone position. The bit value of the k" position of each register is fedinto the first position of each of the succeeding or higher orderregister columns. At the end of this shift cycle, each column is arerequired. The final product is obtained at the outregister positioncontains the value of the second bit put of the multi-operand addercircuitry after a final position of the multiplicand, and immediatelybelow carry-look-ahead addition which combines the results that theregister contains the value of the low-order bit of the finalmulti-operand addition and the results of of the multiplicand, etc.Accordingly, each succeeding the previous multiply cycle. 5 columncontains all the information of the preceding In the present invention,with m representing the column plus one more bit position. Thischaracteristic number of bits in the multiplier and n representing theallows the present invention to be modified so as to atnumber of bits inthe multiplicand, the PPA comprises tain a significant reduction in thenumber of required m rows and m n-l columns, where each row i registerpositions in the intermediate hardware case. shifted one bit to the leftof the previous row in order Th y li l nature of the binary informationgenerated to take into account the arithmetic weight of the multiin thePahtial Product array allows an intermediate plier bit corresponding toits associated row. ti-operand adder r r implementation- A partialproduct is simultaneously generated in the In terms of mathematicalrelations, the following PPA. Since the value of each bit position of abina table illustrates the variations of structural design number iseither 0 or 1, the product of a 0 or l times which can be employed toimplement the present inthe multiplicand will either be a O or thebinary value vention.

Hardware Number of shifts Register columns requirement Speed MaximumMinimum.

"liiienii diate l l intermediate Kt variable.

"3T:TTTn -F'F TITII'I l iiiifitipfieand Minimum Maximum.

shift register.

of the multiplicand itself. Thus, the partial pro cl i ict I For theintermediate case, the register colarray is capable of beingsimultaneously filled by allowumns of partial product array is p, wherem is the length ing a register position in each predetermined kewed ofthe multiplier in bits, n is the length of multiplicand row to bealtered for each bit of the multiplicand. Addiin bits, and k is aninteger greater than or equal to log tionally, an input is applied tothe appropriate register (ml position of each row corresponding to themultiplicand A h one d of th spectrum, the maximum bits. The output ofeach register position may th he amount of hardware results in thefastest computation logically comhihedi for example, y ah AND Operation,time. Implementation of case 1 of the table requires m Whh the pp pmultiplier bit in Order to yield the n-l register columns with theoutputs applied simultrue value of that particular bit by bitmultiplication. taneously to m multi operand adders.

The true values obtained in each column are then sim implementationrequires p register mullaneously apphed to a m-9 adder order columnswhere the output signal generated from all the to yield the results ofthe multiplication operation. Ac- 40 Columns are simultaneously appliedto the Same l h" the mvemlon requlres that (I) the ber of multi-operandadders. However, in this implemumpher l mumphcands be s electwelystored; and mentation, some repetition is required since as the col- (2)the Rama] F array sllnultaneousllf formed umn information is beingapplied to the adder, addition by applymg the multlpllcand busappropnate is simultaneously taking place and each column is being iproduct array g l positions; as logically deter shifted up one position.Thus, the top most bit value is mmild by the mumpher bus; d the Outputsof the lost and then added at the bottom of the column regispamalproduct army be combined m a mum-operand ter to the value found in thek" position ofa column imadder.

. mediately to the right. The resultant information in If the PPA islmplmemed so ab to allow It Physk each column register now correspondsto that which cally handle fewer bits than the number of bits in thewould normally be found in the next ad acent column multiplier, themultiplication process in the partial had the partial product array beenimplemented with m product array must be repeated for each group of then-l register columns.

partitioned multiplier. 7 AW not? f. H

As will be described in greater detail with one particgi er i O thelmplememauoni P ular embodiment, the partial product array of theprescewa e at product array can d mented with a single register column.However, instead ent invention generates numbers which are cyclical innature, since each row is a repeat of the multiplicands, of /T Sh'fts toPerform Complete multiplication, this implementation requires m n-lshifted one position with respect to each preceding row. Thus eachColumn is also Cyclical in nature, Len shifts. In this implementation, ashift into the bottom the right-hand or the least-significant columncontains posltlorl of a feglster l Supplles an appmPr'ate multiplicandbit for the particular cycle or iteration of the low-order position ofthe multiplicand at the top of the register. In the next or adjacentcolumn to the left, the multlphcanoh Process bfimg performed- Thls tremeimplementation requires minimum hardware,

the top register position contains the next higher order multiplicandbit, and immediately below it, the lowbut oh the other hand, wouldrequire ah excessive order bit of the multiplicand is stored in the nextregis- 9 of computatloh timer 7 V ter position. The third columncontains at the topmost Now referringTJFTG. 1, it illustrates thelong-hand position a binary bit from the third position from the processor procedure for the general case of multiplyright of the multiplicand,immediately below it and the ing an n-bit number by an m-bit number.Once the numerical partial product array is established, the product isobtained by numerical row summation in order to generate a finalproduct. Accordingly, it can be seen that this type of multiplicationscheme is ideally suited for implementation with adder circuitry whichis capable of adding multiple operands. Numerous multiple operand addersexist for performing this addition, one such multiple operand adder isdescribed in U.S. Pat. No. 3,675,001, issued July 4, 1972 and assignedto the same assignee as the present invention. WM

FIGS. 3A and 3B illustrate a schematic block diagram illustrating onemanner of structurally implementing the present invention correspondingto the mathematical model given in FIG. 1.

A 9-bit multiplicand number a() a(8) is stored in a multiplicandregister 10. A 6-bit multiplier number b(0) b(5) is stored in multiplierregister 12.

The partial product array (PPA) comprises fourteen register columns andeach register column comprises 6 storage positions each generallydepicted at 14. Outputs [a(0) a(8)] from a multiplicand register 10 areapplied to selected storage positions I0 as illustrated in FIGS. 3A, 3B.The outputs from selected storage positions 14 are gated throughpredetermined AND gates, generally designated at 20, as determined bygating signals received from the plurality of outputs from a multiplierregister 12. The selective gating of AND gates furnish the bit-by-bitmultiplication of the multiplicand stored in register 10 by themultiplier number stored in the register 12.

If the multiplier bit is constituted by a binary l, the

corresponding multiplicand bits will be gated through its associated ANDgate 20 and to an output line generally designated 24.

If the multiplier bit is constituted by a binary 0, then the result ofthe multiplication is represented by a plurality of binary Os beinggated to the associated output line 24, independent of whether themultiplicand bits are binary Os or binary ls. For example, if amultiplicand binary bit 0 stored in multiplicand register position isapplied to the top right-hand storage location 26 (FIG. 3B), and abinary 0 is applied on line 27 from the b(O) location in multiplierregister 12, then a logical AND operation gates a binary O to itsrespective output line 24. The rest of the information is gated in asimilar manner so as to supply the results via the plurality of outputlines 24 to a multi-operand adder 30. The IPA hardware thus generates aplurality of signals which are summed in the adder 30 so as to generatea final product on the plurality of output lines 32.

Summarizing, the multiplicand and multiplier bit positions are placed intheir appropriate registers 10 and 12, respectively. The multiplicandbits are then selectively loaded into their appropriate registerlocations 14. The contents of the register locations 14 are selectivelygated via an associated AND gate 20 in accordance with the multiplierbits [12(0) A b(5) stored in the multiplier register 12. A final productis obtained on output lines 32 from the multioperand adder 30.

Now referring to FIG. 2, it illustrates a mathematical model whichexplains the manner of implementing the PPA and multi-operand adder inaccordance with the present invention in a manner which requires lesshardware, as specifically illustrated in FIG. 4. The skewed nature ofthe long-hand multiplication process as illustrated in FIG. 2 allows thePPA to be arranged so that each cell comprises a three-bit shiftregister and an associated AND gate. This embodiment requires the samesize partial product array previously describedin FIG. 3A and 38;however, only five multi-operand adders are required in order to obtainthe final product or sum. In this instance, m represents the number ofbits in the multiplicand and is specifically illustrated as 9, and ndesignates the number of bits in the multiplier and corresponds to 6.Finally, k is an interger greater than or equal to log (ml or in thisspecific example, log 8=3. The number of required multi-operand addersis given by p, or 5 in this example.

A multiplicand register 40 stores a 9-bit, a(0) a(8) multiplicand and amultiplier register 42 stores a 6-bit, b(O) b(S) multiplier, as wasspecifically illustrated in the embodiment of FIG. 3. In thisembodiment, the PPA rows are grouped into 3-bit partitions, that is,each row comprises five 3-bit shift registers generally designated at44. The plurality of multiplicand bits from the multiplicand register 40are applied via a plurality of output lines sequentially numberedstarting at the low order position as 46, 48, 50, 52, 54, 56, 58, 60 and62. These output lines supply input gating signals to predetermined ANDgates generally indicated at 64. The other input to the plurality of ANDgates 64 receives gating signals via the plurality of output lines 70,72, 74, 76, 78 and 80 from the multiplier register 42, corresponding tothe [17(0) 12(5)] bits. The information stored in the extreme left-handstorage position for each of the plurality of registers 44 is appliedvia a plurality of lines 82, 84, 86, 88 and to its associated one offive multi-operand adders generally indicated at 92.

The outputs generated on the plurality of output lines 82, 84, 86, 88and 90 are applied to the multi-opcrand adders according to theirnumerical weight, thus, they are grouped in accordance with the verticalcolumn from which the information is received, i.e., the mostsignificant bits being applied beginning at the extreme left.

After the partial product array is selectively personalized or writteninto in accordance with the bit positions contained in the multiplierregister 42 and the multiplicand register 40, the output informationstored in the extreme left-hand column is shifted from its associatedleft-hand storage position and fed via line 82 to its associatedmulti-operand adder connected thereto.

The contents of each of the shift registers 44 in that column are thenshifted one position to the left. Next, the outputs from the extremeleft-hand storage position in each of the shift registers 44 situated inthe second column from the left are then fed via line 84 to itsassociated multi-operand adder. The results applied via line 84 are thenadded to the results previously obtained from line 82.

In a similar manner, the contents in each of the shift registers 44 inthe column to the right are shifted to the left another bit position andthen the information stored in the extreme left-hand storage positionfrom each of the registers 44 read out on its associated output lines86, 88 and 90. These results are sequentially added to the resultspreviously obtained.

Now referring to FIG. 5, it illustrates the cyclic nature of the partialproduct numerical array which is generated in the partial product arrayhardware of the present invention. As seen from FIG. 5, the mathematicalmodel contains a complete numerical partial product array as a result ofmultiplying a 9-bit multiplicand by a 6-bit multiplier, mathematicallydesignated as [11(0) a(8)] and [11(0) b(6)], respectively. Every thirdcolumn as designated by the rectangles 91,

numbers generated in the array. Every second and third column in thefive distinct groups (each labelled 1, 2, 3) is obtainable byselectively shifting a predetermined column 1 set of information up oneposition. For example, referring to the information stored in column 1and designated by rectangle 94, it contains information ranging froma(8) in the uppermost storage position down to a(3) in its lowermoststorage position. If the contents of the information stored in block 94is shifted upwards, then the information in the uppermost storagelocation, a(8), is allowed to overflow, and thus the a(7) information isstored in the uppermost location, a(6) is stored in the next touppermost position, down to the information a(3) being stored in thenext to bottom position. The lowermost position is filled withinformation taken from the third from the bottom position of column 93via line 99. Accordingly, the information in register or position 94 nowcontains the identical information to that contained in its adjacentcolumn 2 of the same group, namely, a(7) .a(2). Similarly, the valuesfor each of the number 3 columns in the distinct groups are obtainablefrom a column 1 position by another upward shift and transfer from theright.

The cyclic nature of the information generated in the partial productarray allows a one-third hardware reduction to that previously describedin the embodiments shown in FIGS. 3A, 3B and FIG. 4. This is possiblebecause one register column may be utilized to producc, in timesequence, the information previously contained in three registercolumns. This implementation is mathematically designated by therelationship that the number of register columns necessary for anintermediate hardware implementation is p, or 5 in this specificexample.

FIG. 6 illustrates a hardware implementation in accordance with thisprinciple. A multiplicand register 118 stores a multiplicand comprisingbits a(O) .a(8) which are applied via the plurality of output lines 100,102, 104, 106, 108, 110, 112, 114 and 116, respectively, correspondingtoa sequential numbering beginning at the low order bit.

Similarly, a multiplier register 120 is adapted to receive themultiplier bits 12(0) b(5) and apply them to a plurality of output lines122, 124, 126, 128, 130 and 132, respectively. Each of the five columns140, 142, 144, 146 and 148 comprise a six-stage shift register, eachstorage location being generally designated at 150.

Each of the register positions 150 are adapted to supply a gating signalto an associated AND gate generally designated at 160. Another gatingsignal is applied to selective rows of AND gates 160 via its associatedline (122 132) connected to the multiplier register 120.

The number generated at the output terminals from each of the respectiveAND gates 160 is the product of an associated multiplier andmultiplicand bit position. For example, the product of the a(2) bit andthe b(0) bit is represented by the binary signal on output line 170 fromthe uppermost right-hand AND gate. The outputs from each of the ANDgates 160 are selectively applied to an associated multi-operand addervia lines 180, 182, 184, 186 and 188.

operationally, the partial product array of FIG. 6 in combination withfive multi-operand adders generally depicted at 190 generate a finalproduct in the following manner. The bit positions for the multiplicandand multiplier are loaded into their associated registers 118 and 120,respectively. Then, the information is selectively stored in theplurality of register positions designated 150. This information is thenselectively gated to its respective AND gate and applied to itsassociated multi-operand adder via lines 180, 182, 184, 186 and 188. Theregister columns 140, 142, etc. are shifted up one position and thebottom register position is fed from a third register position from thebottom of a register column immediately to the right; for example, vialine 191. This alteration yields the least partial product arraynumerical values required for the attendant next addition cycle. Outputlines 188 applied partial product results to the multi-operand adder 190in order to initiate an addition operation with the previously storedpartial product result. This sequence is performed a third cycle time soas to yield a final product for this multiplication operation. Forpurposes of clarity, the details of the logic circuitry necessary toselectively alter the partial product value information on adjacentcolumns is not shown, but again is illustrated in schematic form by line191.

Now referring to FIG. 7, it illustrates in greater detail a completemultiplication scheme-including the partial product array means of thepresent invention in combination with a multi-operand adder. In thespecific example, the multiplier is selected as having the capacity ofmultiplying 36 multiplicand bits by 36 multiplier bits, and comprises amultiplicand register 200 adapted to supply multiplicand bits A A to apartial product array means 202, and a multiplier register 204 adaptedto supply a plurality of multiplier bits [2,, b;, via a plurality ofoutput lines to the partial product array means 202.

The partial product array means 202 can be implementable in accordancewith any of the above previously mentioned embodiments. In the mostgeneralized case, the partial product array means 202 would contain 36rows and 7] register columns, if implemented according to the multiplierdescribed in connection with FIGS. 3A and 38. If implemented inaccordance with the partial product array described in connection withFIG. 4, that is a partitioned partial product array, it would contain 9rows and 44 register columns, and would require four cycles through thepartial product array in order to apply all of the 36 bits of themultiplier, that is 9 bits at a time, in order to selectively gate withits associated multiplicand bits.

In the overall multiplier scheme described in detail in FIG. 7, thepartial product array is implemented in accordance with the partialproduct array embodiment previously described in connection with FIG. 6.Thus, only 15 9-bit register columns and the appropriate AND gates arerequired in order to form the partial product array 202. The outputsgenerated from the partial product array 202 are applied via a pluralityof output lines generally designated at 210 to a multioperand adder 212.Again, the details of one such suitable multi-operand adder aredescribed in US. Pat. No. 3,675,001. Generally, the adder 212 comprisesfifteen multiple operand adders (MOA) generally designated 216 and apair of registers comprising an S register and an S register.

- A pair of AND gates 220 and 224 are operative to gate the contents ofthe adder results stored in the S register and S register into a finalcarry-look-ahead adder 224 via respective interconnected OR gates 226and 228. A pair of registers 229 and 230 store partial resultsdesignated R1 and R2 received from the carry- 9 look-ahead adder 224. Inconjunction with a gating signal GATE R1 applied to line 240, thecontents R1 of register 229 are gated through AND gate 244, OR gate 226,and back to the adder 224 for addition with serially received partialproducts generated from adder 212. Similarly, the contents R2 ofregister 230 are gated via AND gate 241, OR gate 228, and back to adder224 upon the application of a gating signal GATE R2 on line 250. Thefinal product of the overall multiplication process is contained inregister 230.

For the particular example of a 36 X 36 bit multiplication, four passesthrough the partial product array 202 are required, which correspond toa l2-cycle operation since each pass requires three applications ofinputs to the multi-operand adders generally designated at 216.

Specifically, the multiplier operates as follows:

1. The multiplicand low order and the 9 multiplier bits are entered intotheir respective registers 200 and 204.

2. The multiplicand is applied to the partial product array 202 in aparallel mode operation for all nine rows.

3. The S and S registers of the adder 212 are filled after three cyclesof operation of the multiplier.

a. On the first cycle, the bits in each column of the partial productarray 202 are applied to their re spective 9-bit multiple operand adders216.

b. At the start of the second cycle, the register columns of the partialproduct array (not shown) are advanced up one position and fed from arighthand adjacent register column, as previously described. At theconclusion of the second cycle, the 9 bits of each of the registercolumns are applied to their respective 9-bit adders 216.

e. The third cycle is a repeat of the second cycle.

4. The S and S, registers now contain a partial result. The contents ofthe S and S registers are combined in the carry-look-ahead adder 224.The result is placed in the register 229. Then, the contents of register229 is added to the contents of register 230 in the carry-lookaheadadder 244 with the most significant bit position contained in theregister 230 being positioned as a ninth bit with respect to the leastsignificant bit contained in the register 229. The contents stored inregister 229 is left justified (adjusted so that the most significantbit is at the leftmost register position) as it is recycled to the adder224 via AND gate 244 and OR gate 226. Then, the addition takes place incarry-look-ahead adder 224 and the results are placed in register R2 areleft justified.

5. Then, in a parallel or overlap mode of operation, the operations ofstep 4 are repeated during a second pass through the partial productarray 202. The multiplicand bits from the multiplicand register 200remain the same, but during this pass, the second nine bits of themultiplier stored in register 204 are applied to the partial productarray 202. This sequence basically comprises a repeat of steps 1, 2 and3 in parallel with the previously described step 4.

6. All the steps of step 4 are again repeated during the second pass. 7.Steps 5, 6 are repeated and overlapped with step 6 for the third ninebits of the multiplier supplied from the multiplier register 204.

8. All the steps previously specified in step 4 are repeated for thethird pass.

9. Step 7 is repeated and overlapped with step 8 for the fourth ninebits of the multiplier applied fromthe 10, multiplier registers 204 tothe partial product array 2( )2.

10. Step 4 is completely repeated during the fourth pass. 1 l Thecontents of register 230 now contain the final product.

if another multiplication is required, it can be overlapped with step10. This results in a l2-cycle multiplication (12 passes through theplurality of multioperand adders 216).

Although the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:

1. A multiplier advantageously adaptable for implementation with largescale integrated circuits comprising;

a. a multiplicand storage means for storing n multiplicand bits of data,and a multiplier storage means for storing m multiplier bits of data,

b. a partial product storage means for generating a partial productincluding no more than m nl storage columns, said partial productstorage means being connected to said multiplicand storage means in-onecoordinate direction associated with said partial product storage means,and also being connected to said multiplier storage means in the othercoordinate direction associated with said partial product storage means,

c. p (m n-l)/k I multi-operand adders connected to said storage array,where k is an integer equal to or greater than log (m-l and where l mn-l// I is an integer greater than or equal to (m n-l )/k,

d. said partial product storage means being selectively responsive tosaid In and n bits of data for generating a partial product, and

6. said 2 multi-operand adders being responsive to said generatedpartial product, independent of said In and n bits of data initiallystored in said multiplier and multiplicand storage means, for generatinga final product.

2. A multiplier advantageously adaptable for implementation with largescale integrated circuits as in claim 1 wherein said partial productstorage means further includes:

a. a plurality of first gating means connected to said storage columns,each of said plurality of first gating means including a first inputterminal, a second input terminal, and an output terminal, a pluralityof said first terminals being connected to said multiplicand storagemeans and a plurality of said second terminals being connected to saidmultiplier storage means, and a plurality of said output terminals beingconnected to predetermined ones of said storage columns, and

b. said plurality of first gating means being selectively responsive tosaid m and n bits of data for storing a partial product in said storagearray.

3. A multiplier advantageously adaptable for implementation with largescale integrated circuits as in claim 1 wherein:

a. said partial product storage means is limited to p storage colurnns,each one otlsaid gstorage colb. said partial product storage meansfurther include means for interconnecting selected storage positionsbetween said storage columns and being responsive to the transfer ofdata on said means for interconnecting for successively generatingpredetermined altered skewed patterns of data independent of said n bitsof data initially stored in said multiplicand storage means, and aplurality of gating means connected to predetermined storage positionsand to said multiplier storage means, said plurality of gating meansbeing responsive to said m multiplier bits of data and seriallyresponsive firstly to said initial predetermined skewed pattern of saidn multiplicand bits of data, and then to said predetermined alteredskewed patterns of data independent of said n bits of data initiallystored in said multiplicand storage means, for generating a plurality ofreduced partial product patterns of data, and

c. said p multi-operand adders being selectively responsive only to saidreduced partial product patterns of data, independent of said m and nbits of data initially stored in said multiplier and multiplicandstorage means, for generating a final product.

4. A multiplier advantageously adaptable for implementation with largescale integrated circuits as in Claim 3 wherein:

data.

1. A multiplier advantageously adaptable for implementation with largescale integrated circuits comprising: a. a multiplicand storage meansfor storing n multiplicand bits of data, and a multiplier storage meansfor storing m multiplier bits of data, b. a partial product storagemeans for generating a partial product including no more than m + n-1storage columns, said partial product storage means being connected tosaid multiplicand storage means in one coordinate direction associatedwith said partial product storage means, and also being connected tosaid multiplier storage means in the other coordinate directionassociated with said partial product storage means, c. p (m + n-1)/kmulti-operand adders connected to said storage array, where k is aninteger equal to or greater than log2 (m-1), and where m + n-1/k is aninteger greater than or equal to (m + n-1)/k, d. said partial productstorage means being selectively responsive to said m and n bits of datafor generating a partial product, and e. said p multi-operand addersbeing responsive to said generated partial product, independent of saidm and n bits of data initially stored in said multiplier andmultiplicand storage means, for generating a final product.
 2. Amultiplier advantageously adaptable for implementation with large scaleintegrated circuits as in claim 1 wherein said partial product storagemeans further includes: a. a plurality of first gating means connectedto said storage columns, each of said plurality of first gating meansincluding a first input terminal, a second input terminal, and an outputterminal, a plurality of said first terminals being connected to saidmultiplicand storage means and a plurality of said second terminalsbeing connected to said multiplier storage means, and a plurality ofsaid output terminals being connected to predetermined ones of saidstorage columns, and b. said plurality of first gating means beingselectively responsive to said m and n bits of data for storing apartial product in said storage array.
 3. A multiplier advantageouslyadaptable for implementation with large scale integrated circuits as inclaim 1 wherein: a. said partial product storage means is limited to pstorage columns, each one of said p storage columns having a pluralityof storage locations and being responsive to said n multiplicand bits ofdata for storing an initial predetermined skewed pattern of said nmultiplicand bits of data, b. said partial product storage means furtherinclude means for interconnecting selected storage positions betweensaid storage columns and being responsive to the transfer of data onsaid means for interconnecting for successively generating predeterminedaltered skewed patterns of data independent of said n bits of datainitially stored in said multiplicand storage means, and a plurality ofgating means connected to predetermined storage positions and to saidmultiplier storage means, said plurality of gating means beingresponsive to said m multiplier bits of data and serially responsivefirstly to said initial predetermined skewed pattern of said nmultiplicand bits of data, and then to said predetermined altered skewedpatterns of data independent of said n bits of data initially stored insaid multiplicand storage means, for generating a plurality of reducedpartial product patterns of data, and c. said p multi-operand addersbeing selectively responsive only to said reduced partial productpatterns of data, independent of said m and n bits of data initiallystored in said multiplier and multiplicand storage means, for generatinga final product.
 4. A multiplier advantageously adaptable forimplementation with large scale integrated circuits as in Claim 3wherein: a. said storage positions comprise a plurality of shiftregister locations distributed among said p storage columns, and b. saidmeans for interconnecting selected storage positions further compriseshifting means connected between predetermined ones of said shiftregister locations for selectively transferring data between said pstorage columns for generating said predetermined altered skewedpatterns of data from said initial predetermined skewed pattern of data.